1. Field of the Invention
The present invention relates to a dynamic random-access memory constituted by employing insulated-gate field-effect transistors.
2. Description of the Prior Art
Having such a great merit because a large capacity is available and the power consumption is low, dynamic random-access memories are widely utilized.
The stored data is maintained in the form of a preservation of an electric charge in each of a plurality of memory cells, e.g., the preservation of the electric charge is stored in a capacitor, in such D-RAMs; hence, the stored data disappears with the elapse of time. Therefore, it is necessary to effect a refreshing operation so that, after data is written into each memory cell, the data is rewritten within a maximum period of time and, thus, the data can be maintained without disappearing. In D-RAMs of a general matrix arrangement where each memory cell is disposed at the intersection between a word line and a digit line, refreshing is performed per word line, so that a single refreshing causes the contents of all the memory cells coupled to a word line to be simultaneously refreshed. Accordingly, the word line address is called the refresh address. Because of the need for such refreshing, all the refresh addresses must be refreshed in a cycle of a given refresh interval (2 mS in general).
A means for refresh control is, therefore, provided on the board system equipped with a memory IC. Employed for the refresh control are generally 5 to 6 ICs for constituting a refresh timing generator and the like. Consequently, although it is possible to neglect the space occupied by the refresh control means, in case of a large-sized board system, the rate of occupation by the refresh control means increases as the system becomes smaller in size, resulting in a decrease in the packaging efficiency. Consequently, dynamic RAMs have been proposed so that the refresh function part is incorporated into a memory chip. A refresh control clock signal (referred to at "RFSH" hereinafter) is provided as an external input pin so that feeding the clock according to the prescribed conditions permits refreshing to be automatically effected inside the chip. Such memories are also called quasi-static RAMs since they can be handled in the same manner that static RAMs are handled as long as the RFSH input conditions are maintained.
In the RAMs, the refresh address designated by the internal refresh adress counter is refreshed by making the RFSH low, without employing any address from the outside. The refreshing is continously performed with respect to different refresh addresses by making the refresh address counter incremental in order as long as the RFSH is low. However, the supply current required for internal refreshing is several mA, which is a large value considering that the RAM is backed up by means of a battery. Consequently, it is difficult to constitute a system having a memory backup function by employing such a quasi-static RAM.